In general, an electronic device including a semiconductor memory device needs a memory control circuit for controlling the semiconductor memory device. In order to meet the timing specification related to the memory control circuit and improve the performance of the electronic device, technologies for high-speed operation and high-speed interface are applied to the semiconductor memory device. For example, a synchronous semiconductor memory device interfacing with the memory control circuit in synchronization with a system bus has been developed.
Also, in order to improve the performance of the semiconductor memory device, the amount of data inputted/outputted per unit time should be increased. Therefore, a configuration of a data input/output line which couples the semiconductor memory device to the outside also serves an important factor for the improvement in the performance of the semiconductor memory device.
Further, in general, a highly-integrated semiconductor memory device includes a plurality of banks sharing a global input/output line through which data are inputted and outputted. The respective banks, included in the semiconductor memory device configured in such a manner, input and output data through the shared global input/output line during a read operation and a write operation.
FIG. 1 illustrates data paths when a known semiconductor memory device performs read and write operations, respectively. Referring to FIG. 1, the data paths will be described as follows.
When the read operation is performed, data stored in a memory cell included in a bank BANK is sensed, amplified and then loaded into a local input/output line pair LIO and LIOB, and an input/output line sense amplifier IOSA amplifies the data loaded into the local input/output line pair LIO and LIOB and outputs the amplified data to the outside of the semiconductor memory device through a global input/output line pair GIO and GIOB.
When the write operation is performed, data inputted from outside is loaded into the global input/output line pair GIO and GIOB, and a write driver WDRV amplifies the data loaded into the global input/output line pair GIO and GIOB and stores the amplified data in a memory cell included in the bank BANK through the local input/output line pair LIO and LIOB.
As described above, the known semiconductor memory device include the write driver WDRV for amplifying data loaded into the global input/output line pair GIO and GIOB during the write operation and the input/output line sense amplifier IOSA for amplifying data loaded into the local input/output line pair LIO and LIOB during the read operation, for each bank. Therefore, the write driver WDRV and the input/output sense amplifier IOSA are separately provided for each bank included in the semiconductor memory device.